On July 23, 2026, AMD CEO Lisa Su took the stage at San Francisco’s Moscone Center for the Advancing AI keynote and introduced the AMD Helios rack-scale AI system. At its core is a single rack packing 72 Instinct MI455X GPUs, 31 TB of pooled HBM4 memory, and AMD-rated performance of 2.9 exaflops FP4 inference and 1.4 exaflops FP8 training per rack—all vendor-reported figures not yet independently benchmarked.
The customer roster announced on stage is substantial. Microsoft Azure, Oracle, OpenAI, and Meta are confirmed early Helios customers. OpenAI CEO Sam Altman joined Su on stage; OpenAI and Meta together have committed to a combined 12 gigawatts of AMD accelerator capacity. Oracle is building a 50,000-GPU supercluster using AMD’s CDNA 5 accelerators. These are announced capacity commitments, not verified delivery receipts.
Inside the MI455X: The GPU at the Core of Helios
The MI455X is built on AMD’s CDNA 5 architecture using TSMC N2 compute chiplets. Each GPU packages two compute dies (GCDs) alongside 16 stacks of HBM4, giving it 432 GB of memory per accelerator and an AMD-claimed 19.6 TB/s of memory bandwidth—both vendor-reported. At 72 GPUs per rack, that stacks to 31 TB of aggregate HBM4.
What AMD has not disclosed: the MI455X’s compute unit count and full die specifications beyond the two-GCD, 16-HBM4-stack package description shown at CES 2026. No official product brief or data sheet with complete CU counts has been published as of the keynote date. ROCm 7, AMD’s software stack, officially supports the FP8, FP6, and FP4 datatypes the MI455X targets for inference workloads, with ROCm 7.2.4 as the current stable release as of May 29, 2026.
How a Rack-Scale System Is Actually Built
Helios is not a single boxed product you order and rack. AMD describes it as a design blueprint for system vendors and OCP-compliant integrators, similar in spirit to how open compute chassis specs work. The physical layout uses 18 compute trays, each holding four MI455X GPUs and one EPYC Venice CPU.
That tray-and-blueprint approach matters for the supply chain. Engineering samples are shipping in H2 2026, with mass production targeted for Q2 2027. AMD says Helios ships to named hyperscale customers in H2 2026; broader enterprise availability is not confirmed, and HBM4 supply is reportedly fully allocated to hyperscalers through 2026.
Every tray’s CPU is the EPYC Venice, the first HPC product in volume production on TSMC’s 2nm Gate-All-Around nanosheet process. Venice offers up to 256 Zen 6 cores, an AMD-claimed performance increase of more than 70% over the previous EPYC Turin generation, doubled memory bandwidth to 1.6 TB/s, and doubled CPU-to-GPU bandwidth.
HBM4 and Why Memory Subsystem Design Defines Rack Performance
HBM—High Bandwidth Memory—stacks DRAM dies vertically and connects them through a silicon interposer directly beside the GPU compute die, dramatically shortening the electrical path and widening the data bus compared to GDDR. Each new HBM generation roughly doubles per-stack bandwidth. HBM4, used by the MI455X, represents the current leading edge of that curve.
For large-model inference and training, raw GPU count is a misleading proxy for capability. What ultimately determines whether a rack can hold and efficiently serve a frontier-scale model is aggregate memory capacity and how fast data moves between memory and compute. Helios’s 31 TB of pooled HBM4—compared to Nvidia’s vendor-stated 20.7 TB for the competing Vera Rubin NVL72—means the rack can keep a substantially larger model fully resident without swapping layers across slower interconnects. AMD also claims 260 TB/s of aggregate scale-up interconnect bandwidth across the rack, which governs how quickly GPUs can share activations during training.
Scale-Up vs. Scale-Out: The Two Networking Layers Every AI Rack Needs
AI infrastructure uses two distinct networking tiers, and confusing them is a common source of miscommunication about system performance. Scale-up networking connects GPUs within a rack at nanosecond-to-microsecond latency, enabling direct GPU memory sharing and making tensor parallelism—splitting a single large model across many GPUs simultaneously—practical. Helios delivers a vendor-reported 260 TB/s of scale-up bandwidth for this purpose.
Scale-out networking connects racks to one another across a cluster. Latency is higher, bandwidth per node lower, but the aggregate reach spans thousands of nodes and supports data parallelism—feeding different training batches to different racks in parallel. Helios provides a vendor-reported 43 TB/s of scale-out Ethernet bandwidth for inter-rack communication. These two tiers are complementary, not interchangeable; a rack optimized for one does not substitute for the other.
UALink vs. NVLink: Open Standard vs. Proprietary Interconnect
Helios uses UALink (Ultra Accelerator Link) for intra-rack scale-up GPU-to-GPU communication. UALink 1.0 was ratified on April 8, 2025 by a consortium that includes AMD, Broadcom, Cisco, Google, HPE, Intel, Meta, and Microsoft. Version 2.0 was published April 7, 2026. Any vendor can implement the spec without licensing fees.
Nvidia’s NVLink 6, used in the Vera Rubin NVL72, is proprietary: Nvidia designs and controls it, and Reuters has reported that Nvidia has recently begun licensing the technology to some partners under pressure from rivals—though it remains unavailable to general third-party silicon vendors. On raw bandwidth, NVLink 6 and UALink are in the same general range—both Helios and the NVL72 vendor-report 260 TB/s of scale-up bandwidth—but the architectural and competitive implications differ sharply. UALink allows a rack builder to source switches, NICs, and future accelerators from multiple vendors, reducing dependence on a single silicon supplier.
At the keynote, Lisa Su made AMD’s positioning explicit: “The future of AI is not going to be built by any one company or in a closed ecosystem. It’s going to be shaped by open collaboration across the industry.” For scale-out between racks, Helios uses Ultra Ethernet rather than InfiniBand, consistent with the open-standards posture.
How Helios Stacks Up Against Nvidia’s Vera Rubin NVL72
Putting the vendor-stated specs side by side reveals where each platform’s designers made different tradeoffs.
Nvidia’s Vera Rubin NVL72 packs 72 Rubin GPUs alongside 36 Vera CPUs (custom Arm Olympus cores) and is built on TSMC 3nm for the GPU dies. It carries a vendor-reported 20.7 TB of HBM4 per rack and Nvidia rates it at 3.6 exaflops NVFP4 with 260 TB/s of NVLink 6 scale-up bandwidth.
Helios counters with 31 TB of HBM4—roughly 50% more memory per rack—and AMD rates it at 2.9 exaflops FP4. Both GPU platforms use TSMC’s most advanced nodes, though Helios’s MI455X compute chiplets are on N2 while Rubin is on 3nm.
The critical caveat: AMD rates Helios at 2.9 exaflops FP4 and Nvidia rates the NVL72 at 3.6 exaflops NVFP4, but these figures use vendor-defined precision formats and have not been validated by MLPerf or any independent benchmark as of the keynote date. FP4 and NVFP4 are not identical formats, and the sparsity assumptions behind each rating are not the same, so direct arithmetic comparison is unreliable without independent testing.
Financial analysts and press reports circulating around the keynote cited $5–5.5 million per rack for Helios; AMD has not published an official list price. Google Cloud and AWS have not publicly committed to the platform as of July 23, 2026.
What This Generation of Rack-Scale AI Means for the Industry
The most durable story from the Helios announcement may not be any single spec. It is the combination of open standards—UALink, Ultra Ethernet, OCP-compliant tray design—arriving at the same time as a real alternative software stack. ROCm 7’s HIP runtime now aligns more closely with CUDA Graph behavior and officially targets FP8, FP6, and FP4 inference. AMD vendor-reported a 30% DeepSeek R1 throughput advantage for ROCm 7 on MI355X over Nvidia B200 on CUDA; this has not been independently replicated, and the baseline comparison methodology has been questioned. The software gap is narrowing, but CUDA’s ecosystem depth remains a genuine structural advantage for Nvidia.
For teams evaluating infrastructure decisions today, the practical constraints are straightforward: HBM4 supply is reportedly fully allocated to hyperscalers through 2026, mass production of Helios targets Q2 2027, and no independent benchmark results exist yet for either Helios or the NVL72. Watching MLPerf submissions for both platforms, monitoring ROCm ecosystem maturity for your specific model workloads, and tracking whether UALink adoption spreads beyond AMD’s own hardware are the metrics worth following before committing to either platform.
The broader shift—from proprietary rack-scale stacks toward openly specified interconnects and reference blueprints—is the structural change the Helios announcement represents, regardless of how the benchmark numbers eventually settle.
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FAQ
What is UALink and who supports it?
UALink is an openly licensed GPU-to-GPU interconnect specification for scale-up (intra-rack) communication. Version 1.0 was ratified on April 8, 2025 by a consortium including AMD, Broadcom, Cisco, Google, HPE, Intel, Meta, and Microsoft. Version 2.0 followed on April 7, 2026. Any vendor can implement it without licensing fees, in contrast to Nvidia’s proprietary NVLink.
How does Helios differ from a standard GPU server?
Helios is a rack-scale blueprint—18 trays, each with four MI455X GPUs and one EPYC Venice CPU, yielding 72 GPUs per rack with pooled memory and unified scale-up interconnect. It is designed for OCP-compliant integrators to build from, not a single boxed product customers order directly.
When can enterprises outside the named hyperscalers buy Helios?
AMD says engineering samples ship H2 2026 and mass production targets Q2 2027. Broader enterprise availability is not confirmed, and HBM4 supply is reportedly fully allocated to hyperscalers through 2026.
Are the exaflops comparisons between Helios and Vera Rubin NVL72 reliable?
Not yet. AMD rates Helios at 2.9 exaflops FP4; Nvidia rates the NVL72 at 3.6 exaflops NVFP4. These are vendor-defined precision formats with different sparsity assumptions. Neither platform has MLPerf or independent benchmark results as of July 23, 2026.
Sources
- AMD Investor Relations — CES 2026 Press Release — AMD Investor Relations (primary)
- ROCm Release History — AMD ROCm Documentation (primary)
- UALink Wikipedia — version history and consortium membership — Wikipedia / UALink Consortium (secondary)
- AMD Advancing AI 2026: Helios Rack Hits $5.25M — Tech Insider (secondary)
- AMD begins production ramp of 256-core EPYC Venice — Tom’s Hardware (secondary)
- Nvidia Vera Rubin explained: specs, NVL72 rack, and shipping timeline — Silicon Report (secondary)
- Scale-Up vs. Scale-Out: The Guide to AI Infrastructure Scaling — Engineers Guide / Substack (secondary)
- AMD unveils AI server as OpenAI taps its newest chips — Market Screener / Reuters (secondary)